谁能简单介绍一下AM486系列的处理器
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发布时间：2022-05-24 13:04
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时间：2023-10-14 18:38
n High-Performance Design
— Instry-standard write-back cache support
— Frequent instructions execute in one clock
— 105.6-million bytes/second burst bus at 33 MHz
— Flexible write-through and write-back address
control
— Advanced 0.35-m CMOS-process technology
— Dynamic bus sizing for 8-, 16-, and 32-bit buses
— Supports “soft reset” capability
n High On-Chip Integration
— 16-Kbyte unified code and data cache
— Floating-point unit
— Paged, virtual memory management
n Enhanced System and Power Management
— Stop clock control for reced power
consumption
— Instry-standard two-pin System Management
Interrupt (SMI) for power management independent
of processor operating mode and operating
system
— Static design with Auto Halt power-down support
— Wide range of chipsets supporting SMM available
to allow proct differentiation
n Complete 32-Bit Architecture
— Address and data buses
— All registers
— 8-, 16-, and 32-bit data types
n Standard Features
— 3-V core with 5-V tolerant I/O
— Available in a 133-MHz version
— Binary compatible with all Am486®DX,
Am486DX2, and Am486DX4 microprocessors
— Wide range of chipsets and support available
through the AMD FusionPCSM Program
n 168-pin PGA package or 208-pin SQFP package
n IEEE 1149.1 JTAG Boundary-Scan Compatibility
n Supports Environmental Protection Agency's
Energy Star program
— 3-V operation reces power consumption up to
40%
— Energy management capability provides excellent
base for energy-efficient design
— Works with a variety of energy-efficient, powermanaged
GENERAL DESCRIPTION
The Am5X86™ microprocessor is an addition to the AMD
microprocessor proct family. The new processor enhances
system performance by raising the microprocessor
operating frequency to the highest levels allowed by
current manufacturing technology, while maintaining
complete compatibility with the standard Am486 processor
architecture and Microsoft® Windows®. The CPUs
incorporate write-back cache, flexible clock control, and
enhanced SMM. Table 1 shows available processors
in the Am5X86 microprocessor family.
The Am5X86 microprocessor family allows write-back
configuration through software and cacheable access
control. On-chip cache lines are configurable as either
write-through or write-back. The CPU clock control feature
permits the CPU clock to be stopped under controlled
conditions, allowing reced power consumption
ring system inactivity. The SMM function is implemented
with an instry standard two-pin interface.
Table 1. Clocking Options
Operating
Frequency
Input Clock Available Package
133 MHz 33 MHz 168-pin PGA
133 MHz 33 MHz 208-pin SQFP
PRELIMINARY
Am5X86™
Microprocessor Family
