未来十年的芯片路线图
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发布时间：2024-09-17 08:42
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时间：2024-10-01 11:31
The roadmap includes standard FinFET transistors lasting until the 3nm node, followed by a transition to new fully-gated (GAA) nanosheet designs, which will enter mass production in 2024. Imec has mapped out a route to 2nm and A7 (0.7nm) forksheet designs, followed by A5 and A2 CFET (Complementary FET) and atom channel breakthrough designs.
As technology advances, the cost of transitioning to smaller nodes becomes increasingly expensive, and the traditional method of building single-chip monoliths with large chips has given way to small chips. Small chip-based designs break down various chip functions into different chips that are interconnected, enabling chips to function as cohesive units, albeit with trade-offs.
Imec envisions the CMOS 2.0 paradigm, which includes breaking down chips into smaller parts, separating cache and memory into their own units with different transistors, and stacking them in 3D over other chip functions. This approach will heavily rely on Backside Power Distribution Networks (BPDN), which route all power through the transistors' backside.
Imec's focus is on developing faster, denser transistors. The first wave of this technology will feature Gate All Around (GAA) or nanosheet devices, which made their debut in the 2024 2nm node, replacing the current leading technology, the tri-gate FinFET. GAA transistors offer improvements in transistor density and performance, such as faster transistor switching, while using the same driver current as multiple fins. Leakage is also significantly reduced, as the channel is fully surrounded by the gate.
Several chip manufacturers have adopted this transistor technology in different variations. Industry leader TSMC plans to introduce its GAA N2 node for mass production in 2025. Meanwhile, Intel's "intel 20A" RibbonFET, with four stacked nanosheets, each fully enclosed by a gate, will debut in 2024. Samsung was the first to produce transport products using GAA, but its small-batch SF3E pipe-cleaning node will not see mass production. Instead, Samsung will launch its advanced node for mass production in 2024.
As we look ahead, forksheet transistors are expected to begin from the 1nm (A10) node and continue until the A7 node (0.7nm). This design involves stacking NMOS and PMOS separately but with an electric field barrier to achieve higher performance and/or better density.
Complementary FET (CFET) transistors will appear for the first time at the 1nm (A10) node in 2028, allowing for further reduction of footprint and enabling higher-density standard cell libraries. Eventually, we will see CFET versions with atomic channels, further boosting performance and scalability. CFETs are anticipated to mark the end of nanosheet device scaling and the visible end of the roadmap.
To overcome performance, power, and density scaling obstacles, new technologies will be needed, and imec envisions that this will require a new CMOS 2.0 paradigm and System Technology Co-Optimization (STCO).
STCO involves rethinking the design process by modeling system and target application requirements and using this knowledge to inform design decisions. This approach often leads to "decomposing" functions typically found as part of a single-chip processor, such as power, I/O, and caching, into separate units to optimize each type of transistor for the desired performance characteristics, thereby improving cost efficiency.
Imec envisions that the highest-level goal of STCO is to decompose a standard chip design into its own layers for the high-speed caching/memories, enabling more efficient 3D stacking designs. This requires simplifying the top of the chip stack and transforming the Back End of Line (BEOL) process flow to focus on connecting transistors and facilitating communication and power transmission.
Unlike current designs that transmit power from the chip's top, the BPDN uses Through-Silicon Vias (TSVs) to route all power to the transistors' backside, separating power delivery from the data transmission interconnects on the other side of the normal position. This separation improves droop characteristics, enabling faster transistor switching, while also allowing for more densely packed signal routing at the chip's top. It also has benefits for signal integrity, as simplified wiring can more quickly connect resistors and capacitors.
The ability to move power networks to the chip's bottom makes it easier to perform wafer-to-wafer bonding on the top of the wafer, unlocking the potential to stack memory on top of logic. Imec even envisions that other functionalities could be moved to the wafer's backside, such as global interconnects or clock signals.
Intel has announced its BPDN technology version, called PowerVIA, which will debut in its 2024 intel 20A node. Intel plans to reveal more details about the technology at the upcoming VLSI event. Meanwhile, TSMC will introduce BPDN in its 2026 N2P node production, lagging behind Intel significantly. There are rumors that Samsung will adopt this technology in its 2nm node.
CMOS 2.0: The True Path to 3D Chips
Imec's vision for the future of chip design, encapsulated in the CMOS 2.0 paradigm, covers the full 3D chip design. We've seen AMD's second-generation 3D V-Cache, which stacks memory to increase capacity by placing L3 memory on top of the processor, but Imec envisions the entire cache hierarchy contained within its own layers, with L1, L2, and L3 caches stacked vertically on top of the transistors that make up the processing core of their own chip. Each level of cache will be created using transistors best suited for that task, which is increasingly critical as SRAM scaling slows down.
Reducing the cost of 3D-stacked caches in lower-density nodes may lead to larger caches than we've seen in the past. Proper implementation of 3D stacking can also help mitigate latency issues associated with larger caches.
These CMOS 2.0 technologies will leverage 3D stacking techniques, such as wafer-to-wafer bonding, to form direct chip-to-chip 3D interconnects.
As we've seen in the album above, Imec also has a 3D-SOC roadmap outlining the continuous shrinking of interconnects, leading to faster and more densely packed interconnects in the future. These advancements will be achieved through the use of updated interconnect types and processing methods in the coming years.
