16位循环移位寄存器设计
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发布时间：2022-05-20 21:55
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时间：2024-03-05 16:25
-- SEL: in STD_LOGIC_VECTOR(3 downto 0);
-- B_INPUT: in STD_LOGIC_VECTOR(15 downto 0);
-- B_OUTPUT: out STD_LOGIC_VECTOR(15 downto 0);
--**Insert the following between the 'architecture' and
---'begin' keywords**
signal SEL_A, SEL_B: STD_LOGIC_VECTOR(1 downto 0);
signal C: STD_LOGIC_VECTOR(15 downto 0);
--**Insert the following after the 'begin' keyword**
SEL_A <= SEL(1 downto 0);
SEL_B <= SEL(3 downto 2);
process(SEL_A,B_INPUT)
begin
case SEL_A is
when "00" => --shift by 0
C <= B_INPUT;
when "01" => --shift by 1
C(15) <= B_INPUT(0);
C(14 downto 0) <= B_INPUT(15 downto 1);
when "10" => --shift by 2
C(15 downto 14) <= B_INPUT(1 downto 0);
C(13 downto 0) <= B_INPUT(15 downto 2);
when "11" => --shift by 3
C(15 downto 13) <= B_INPUT(2 downto 0);
C(12 downto 0) <= B_INPUT(15 downto 3);
when others =>
C <= B_INPUT;
end case;
end process;
process(SEL_B,C)
begin
case SEL_B is
when "00" => --shift by 0 more
B_OUTPUT <= C;
when "01" => --shift by 4 more
B_OUTPUT(15 downto 12) <= C(3 downto 0);
B_OUTPUT(11 downto 0) <= C(15 downto 4);
when "10" => --shift by 8 more
B_OUTPUT(15 downto 8) <= C(7 downto 0);
B_OUTPUT(7 downto 0) <= C(15 downto 8);
when "11" => --shift by 12 more
B_OUTPUT(15 downto 4) <= C(11 downto 0);
B_OUTPUT(3 downto 0) <= C(15 downto 12);
when others =>
B_OUTPUT <= C;
end case;
end process;
[DISABLELBCODE]
