VHDL:使用加法实现3位二进制乘法电路(7×4=28)
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发布时间：2022-04-24 06:12
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时间：2023-08-04 06:01
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY Mult IS
GENERIC (n:Positive:=3);
PORT(a,b:IN std_logic_vector(n-1 DOWNTO 0);
y:OUT std_logic_vector(2*n-1 DOWNTO 0));
END Mult;
ARCHITECTURE adder OF Mult IS
BEGIN
PROCESS(a,b)
VARIABLE sum,temp_a:std_logic_vector(2*n-1 DOWNTO 0);
BEGIN
sum := (OTHERS => '0');
FOR i IN 0 TO n-1 LOOP
temp_a := (OTHERS => '0');
temp_a(i+n-1 DOWNTO i) := a;
IF b(i)='1' THEN
sum := sum + temp_a;
END IF;
END LOOP;
y <= sum;
END PROCESS;
END adder;
