用VHDL语言编程~急~

发布网友发布时间：2022-04-24 12:16

共4个回答

热心网友时间：2023-10-12 13:25

1. signal cnt:std_logic_vector(4 downto 0);
process(clk)

if clk'event and clk='1' then
if cnt="2100" then
cnt<="1000";
jinwei<='1';
else cnt<=cnt+1;
end if ;
end if;
end process;
6、b(3)=1;b(0)=0

热心网友时间：2023-10-12 13:26

library ieee;
use ieee.std_logic_1164.all;

entity mux4 is
port(clk : in std_logic;
d0,d1,d2,d3 : in std_logic;
a,b : in std_logic;
q : out std_logic
);
end entity mux4;

architecture s of mux4 is
ab : std_logic_vector(1 downto 0);
begin
ab<=a&b;
process(clk,ab)
if clk'event and clk='1' then
case ab is
when "00" =>
q<=d0;
when "01" =>
q<=d1;
when "10" =>
q<=d2;
when "11" =>
q<=d3;
when others =>
q<='Z';
end case;
end process;
end architecture s;

热心网友时间：2023-10-12 13:26

0分？太扣了吧！不给你说！

热心网友时间：2023-10-12 13:27

楼主我也想要啊！考试题啊！如果有的话可以给我吗？谢谢啦！
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