求高手指导,FPGA产生波形遇到了问题:单个波形可以输出,多个就没法选 ...

发布网友发布时间：2024-07-07 08:17

共3个回答

热心网友时间：2024-07-12 20:24

你把process模块拆成2个进程，一个进程只管地址加1，另一个进程管着a、b的4选1多路选择器。而且地址计数器用一个计数器就可以，没必要用四个。
ARCHITECTURE DACC OF waveall IS
--sin 波形
COMPONENT data_sinrom
PORT(address : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
inclock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT data_fangrom-- 方波
PORT(address : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
inclock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT data_sanrom-- 三角波
PORT(address : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
inclock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT data_juchirom-- 锯齿波
PORT(address : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
inclock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
SIGNAL DATA1,DATA2,DATA3,DATA4:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGANL Q:STD_LOGIC_VECTOR(8 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN Q<=Q+1;
END IF;
END PROCESS;
PROCESS(a,b)
VARIABLE ab:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
ab:=a&b;
CASE ab IS
WHEN "00" => DOUT <= DATA1;
WHEN "01" => DOUT <= DATA2;
WHEN "10" => DOUT <= DATA3;
WHEN "11" => DOUT <= DATA4;
WHEN OTHERS => DOUT <= (OTHERS => 'Z');
END CASE;
END PROCESS;
u1: data_sinrom PORT MAP(address=>Q, q=>DATA1, inclock=>CLK);
u2: data_fangrom PORT MAP(address=>Q, q=>DATA2, inclock=>CLK);
u3: data_sanrom PORT MAP(address=>Q, q=>DATA3, inclock=>CLK);
u4: data_juchirom PORT MAP(address=>Q, q=>DATA4, inclock=>CLK);
END;

热心网友时间：2024-07-12 20:25

把process里的clk去掉试试

热心网友时间：2024-07-12 20:23

VHDL我不是很熟悉，不过我感觉a和b没有用来选择输出，而是用来使能四个计数器了，输出端口接的一直是data_juchirom的输出吧
如果有错，请指教