...异步复位clr和预置控制ld的六进制减法计数器cnt6的VHDL语言_百度知 ...

发布网友发布时间：2024-03-05 18:37

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热心网友时间：2024-03-05 21:58

Library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;
use IEEE.std_logic_unsigned.all;
ENTITY cnt6 IS
PORT(
d : IN std_logic_vector(3 downto 0);
clk : IN std_logic;
clr : IN std_logic;
en : IN std_logic;
ld : IN std_logic;
q : OUT std_logic_vector(3 downto 0)
);
END cnt6;
ARCHITECTURE cnt6_rtl OF cnt6 IS
SIGNAL cnt : std_logic_vector(3 downto 0);
BEGIN
-- counter
PROCESS (clk, clr)
BEGIN
IF (clr = '1') THEN
cnt <= "0000"; --异步复位
ELSIF (clk'EVENT AND clk = '1') THEN
IF (ld = '1') THEN
cnt <= d; --预置数值
ELSE
IF (en = '1') THEN --同步使能
IF (cnt = "0000") THEN
cnt <= "0101"; --减到0时，继续减则变为5
ELSE
cnt <= cnt - 1; --减法
END IF;
END IF;
END IF;
END IF;
END PROCESS;
q <= cnt;
END cnt6_rtl;