VHDL设计上升沿触发的JK触发器
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发布时间：2022-05-05 22:10
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时间：2022-06-28 04:42
use ieee.std_logic_1164.all;
entity jk is
port(j,k,clk: in std_logic;
q,nq: buffer std_logic);
end;
architecture behave of jk is
signal q_s,nq_s:std_logic;
begin
process(j,k,clk)
begin
if(clk'event and clk='1')then
if(j='0')and(k='1')then
q_s<='0';
nq_s<='1';
elsif (j='1')and(k='0')then
q_s<='1';
nq_s<='0';
elsif(j='1')and(k='1')then
q_s<=not q;
nq_s<=not nq;
end if;
end if;
q<=q_s;
nq<=nq_s;
end process;
end;
