verilog HDL8路抢答器课程设计怎么写啊?

发布网友发布时间：2022-07-27 09:08

共1个回答

热心网友时间：2023-10-25 03:59

我刚替别人写的五路的，没调试过，但是ISE11.4综合正确。自己改成8路吧
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:59:03 07/08/2010
// Design Name:
// Mole Name: qiangdaqi
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
mole qiangdaqi(clk,Input1,Input2,Input3,Input4,Input5,Input6,en,LED,beep,LED1,LED2,LED3,LED4,LED5
);
input clk;
input Input1;
input Input2;
input Input3;
input Input4;
input Input5;
input Input6;
input en;
output LED;
output beep;
output LED1;
output LED2;
output LED3;
output LED4;
output LED5;
reg Inputflag;
reg [3:0]cache;
reg beepflag;
reg LED1;
reg LED2;
reg LED3;
reg LED4;
reg LED5;
reg [7:0]LED;
reg beep;
integer i;
always@(posedge clk)
begin
if(en==1)
begin
if(Inputflag==0)
begin
if(Input1==1)
begin
LED1=1;
Inputflag=1;
beep=1;
#100
beep=0;
cache=9;
end
else if(Input2==1)
begin
LED2=1;
Inputflag=1;
beep=1;
#100
beep=0;
cache=9;
end
else if(Input3==1)
begin
LED3=1;
Inputflag=1;
beep=1;
#100
beep=0;
cache=9;
end
else if(Input4==1)
begin
LED4=1;
Inputflag=1;
beep=1;
#100
beep=0;
cache=9;
end
else if(Input5==1)
begin
LED5=1;
Inputflag=1;
beep=1;
#100
beep=0;
cache=9;
end
else
begin

end
end
if(Inputflag==1)
begin
if(i<=100)
begin
i=i+1;
end
else
begin
case(cache)
4'b0000:
begin
LED=8'b11111100;
LED1=0;
LED2=0;
LED3=0;
LED4=0;
LED5=0;
cache=0;
beep=1;
#5
beep=0;
#5
beep=1;
#5
beep=0;
end
4'b0001: LED=8'b01100000;
4'b0010: LED=8'b11011010;
4'b0011: LED=8'b11110010;
4'b0100: LED=8'b01100110;
4'b0101: LED=8'b10110110;
4'b0110: LED=8'b10111110;
4'b0111: LED=8'b11100000;
4'b1000: LED=8'b11111110;
4'b1001: LED=8'b11110110;
default: LED=8'b11111100;
endcase
cache=cache-1;
end
end
end
else
begin
beep=0;
LED=11111100;
i=0;
end
end

endmole