翻译一下这段话,翻译成英语。

发布网友 发布时间：2022-11-27 13:24

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热心网友 时间：2023-10-16 20:59

译码器模块主要是产生16路的分区信号（低电平有效）分别控制16个锁存器，把16个分区的显示数据分别锁存在相应的锁存器中。
The decoder mole partition signal generating 16 Road(active low) to respectively control the 16 latch, the 16partition of the display data are latched corresponding latch.
3.5数据锁存器组及移位寄存器组模块
3.5 data latches and shift register mole
数据锁存器组模块由16个8位锁存器组成锁存器组、锁存16个分区的数据。移位寄存器组模块16个8位寄存器组成,把各路锁存器中8位并行数据转换成同时输出的16路串行数据，驱动LED显示屏，实现数据并转换。
The data latch mole consists of 16 8 bit latch latcheslatch group, 16 partitioned data. Shift register groupmole 16 8 bit registers, the various latch 8 bit parallel data into 16 serial data output at the same time, LED display driver, and realize data conversion.
其生成的元件符号如图6所示。其中，DATA—IN[70] 为每个分区的8位并行数据上输入，SCLK为移位时钟，LOAD为数据锁存信号，CS[150]为16分区的输入信号（接译码器的输出）DATA_OUT[150]为16路的串行数据输出。
The element symbol as shown in figure 6. Among them,DATA IN[70] is a 8 bit parallel data for each partition of theinput, SCLK clock, LOAD as the data latch signal, CS[150] as the input signal of 16 partitions (output of the decoder)DATA_OUT[150] serial data output 16 road.

热心网友 时间：2023-10-16 20:59

译码器模块主要是生产16路的分区信号（低电平有效）分别控制16个锁存器，被16个分区的显示数据分别所存在相应的锁存器中。
The decoder mole is mainly used to proce signal for 16 partitions (valid fo low level voltage), controlling 16 latches. Display data from 16 partitions is saved respectively in corresponding latches.
3.5 数据锁存器组及移位寄存器组模块
Data latches group and shift register group moles
数据锁存器组模块由16个8位锁存器组成锁存器组，锁存16个分区的数据。移位寄存器组模块由16个8位移位寄存器组成，把各路锁存器中8位并行数据转换成同时输出的16路串行数据，驱动LED显示屏，实现数据的并串转换。
Data latches group mole is latches group, made up of 16 8-bit latches, which latches data of 16 partitions. Shift register group moles is made up of 16 8-bit registers, which converts 8-bit parallel data in latches into 16 routes of simultaneously output serial data and drives LED display to achieve the serial conversion of data.
其生成的元件符号如图6所示。其中，DATA_IN[70]为每个分区的8位并行数据输入，SCLK为移位时钟，CLR为清零信号，LOAD为数据锁存信号，CS[150]为16分区的输入信号（接译码器的输出）DATA_OUT[150]为16路的串行数据输出。
Proced componentsymbols are shown as in picture 6. Among them, DATA IN[70] is the 8-bit parallel data input of each partition；SCLK is the shift clock; LOAD is the data latch signal; CS[150] is the input signal(output of the decoder) of 16 partitions and DATA_OUT[150] is the output of 16 routes of serial data.