用verilog hdl设计一个倍频器，不需要综合，使用行为级代码就行，实现3、5、6、10、63倍频
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发布时间：2022-05-12 22:04
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时间：2023-10-25 10:10
input clk , // 输入时钟
input rst , // 复位信号
output reg clk_3div , //3分频时钟
output reg clk_5div , //
output reg clk_6div ,
output reg clk_10div ,
output reg clk_63div
);
reg[2:0] clk_cnt3;
reg[3:0] clk_cnt5;
reg[3:0] clk_cnt6;
reg[4:0] clk_cnt10;
reg[7:0] clk_cnt63;
always@(posedge clk or negedge clk or posedge rst) //3分频
begin
if(rst)
clk_cnt3 <= 3'd0;
else if(clk_cnt3 == 3'd5)
clk_cnt3 <= 3'd0;
else
clk_cnt3 <= clk_cnt3 +3'd1;
end
always@(posedge clk or negedge clk or posedge rst)
begin
if(rst)
clk_3div <= 1'b0;
else if((clk_cnt3 >=0) && (clk_cnt3 < 3))
clk_3div <= 1'b1;
else
clk_3div <= 1'b0;
end
always@(posedge clk or negedge clk or posedge rst) //5分频
begin
if(rst)
clk_cnt5 <= 4'd0;
else if(clk_cnt3 == 4'd9)
clk_cnt5 <= 4'd0;
else
clk_cnt5 <= clk_cnt5 + 4'd1;
end
always@(posedge clk or negedge clk or posedge rst)
begin
if(rst)
clk_5div <= 1'b0;
else if((clk_cnt5 >=0) && (clk_cnt5 < 5))
clk_5div <= 1'b1;
else
clk_5div <= 1'b0;
end
always@(posedge clk or negedge clk or posedge rst) //6分频
begin
if(rst)
clk_cnt6 <= 3'd0;
else if(clk_cnt6 == 4'd11)
clk_cnt6 <= 3'd0;
else
clk_cnt6 <= clk_cnt6 +4'd1;
end
always@(posedge clk or negedge clk or posedge rst)
begin
if(rst)
clk_6div <= 1'b0;
else if((clk_cnt6 >=0) && (clk_cnt6 < 6))
clk_6div <= 1'b1;
else
clk_6div <= 1'b0;
end
always@(posedge clk or negedge clk or posedge rst) //10分频
begin
if(rst)
clk_cnt10 <= 5'd0;
else if(clk_cnt10 == 5'd19)
clk_cnt10 <= 5'd0;
else
clk_cnt10 <= clk_cnt10 +5'd1;
end
always@(posedge clk or negedge clk or posedge rst)
begin
if(rst)
clk_10div <= 1'b0;
else if((clk_cnt10 >=0) && (clk_cnt10 < 10))
clk_10div <= 1'b1;
else
clk_10div <= 1'b0;
end
always@(posedge clk or negedge clk or posedge rst) //63分频
begin
if(rst)
clk_cnt63 <= 8'd0;
else if(clk_cnt63 == 8'd125)
clk_cnt63 <= 8'd0;
else
clk_cnt63 <= clk_cnt63 +8'd1;
end
always@(posedge clk or negedge clk or posedge rst)
begin
if(rst)
clk_63div <= 1'b0;
else if((clk_cnt63 >=0) && (clk_cnt63 < 63))
clk_63div <= 1'b1;
else
clk_63div <= 1'b0;
end
endmole
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时间：2023-10-25 10:11
